One or more embodiments relate to memory device technology and fabrication technology thereof, and more particularly, to a memory device employing a nanotube or nanowire network as a storage component, and a method of fabricating the memory device.
In memory devices used in electronic instruments, some factors to consider are the costs of production, nonvolatility, high-density, low power consumption, etc. Dynamic random access memory (DRAM) devices are commonly used memory devices in electronic instruments and can achieve high speeds and a high degree of integration. However, these devices require periodic refreshing due to their volatile characteristic and thus, they consume large amounts of power. On the other hand, flash memory devices have the advantage of a nonvolatile characteristic, yielding low production costs and low power consumption. Conversely, operating speed is low and information can only be stored for limited amounts of time. Therefore, research for developing a memory device having the advantages of both, the DRAM device and the flash memory device is currently in progress.
Recently, various researches for the development of a memory device using nano technology have been achieved. Specifically, a memory device, which switches between an on state and an off state according to a junction state of nanotubes or nanowires arranged in directions intersecting each other, is disclosed in an article entitled “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing”, released in Vol. 289 of Science Magazine, 2000. In particular, a pair of single-walled carbon nanotubes (SWNTs) arranged in the directions intersecting each other has different junction states, i.e., a separated state (refer to FIG. 1A) or a connected state (refer to FIG. 1B), according to bias coupled thereto. If the pair of nanotubes is separated from each other, current flowing through the pair of nanotubes becomes relatively small and thus the pair of nanotubes has the off state. On the other hand, if the pair of nanotubes is connected to each other, current flowing through the pair of nanotubes becomes relatively great and thus the pair of nanotubes has the on state. As described above, it is possible to fabricate the memory device by using the junction state formed by the pair of nanotubes. Thus, one junction formed by the pair of nanotubes constructs one memory cell. Since the on/off state is maintained although the bias supplied from the external is interrupted, a nonvolatile memory device may be fabricated using such a characteristic. However, mass production of these devices is difficult to achieve due to the problems associated with individual nanotubes or nanowires.
Presently, there is an approach to insert a 3-dimensional network structure, formed by a random arrangement of nanotube or nanowire junction pairs, between an upper electrode and a lower electrode and to construct a memory cell using the network structure as the storage component.
FIGS. 2A and 2B illustrate views of a memory device employing a conventional carbon nanotube network. FIG. 2A describes a storage component of a memory cell. FIG. 2B shows a cell array constructed in a matrix structure, wherein the cell array includes a unit memory cell having the storage component described in FIG. 2A.
Referring to FIG. 2A, the storage component includes a lower electrode 21, an upper electrode 23, and a carbon nanotube network 22 disposed between the lower electrode 21 and the upper electrode 23. Herein, the carbon nanotube network 22 has a pattern with a specific shape.
The carbon nanotube network 22 is constructed with a number of carbon nanotubes arranged in random directions and thus a plurality of junctions is formed among the carbon nanotubes. The plurality of junctions included in the carbon nanotube network 22 is separated or in contact with each other according to bias coupled between the lower electrode 21 and the upper electrode 23. Therefore, the carbon nanotube network 22 shows a bi-stable on/off state as a whole.
FIG. 2B displays a carbon nanotube network arranged in a matrix of a unit memory cells “A”, each unit memory cell having the CNT of the storage component illustrated in FIG. 2A.
A selection device such as the transistor T is positively necessary in order to gain access to a certain memory cess. Therefore, in addition to one carbon nanotube network, CNT, each unit memory cell A includes one transistor T. This is because the carbon nanotube network storage component alone does not have a selection function.
As describe above, since the unit memory cell requires a selection device such as a transistor and a storage component such as a carbon nanotube network, the area occupied by the selection device will deteriorate the degree of integration of the memory device. Furthermore, since a first process of forming the transistor and a second process of forming a contact to achieve the junction with the transistor are required, the fabrication process of the memory device becomes complicated.